1) Field of the Invention
This invention relates generally to fabrication of MOS semiconductor device and more particularly to the fabrication of an elevated source/drain (S/D) for a field effect transistor.
2) Description of the Prior Art
In conventional CMOS processing, the active silicon regions are contacted through openings in the overlying oxide insulating layer. Metal used for forming electrical contacts must overlay these openings sufficiently to prevent damage to the active regions during patterning of the metal. Furthermore, the active source and drain regions must be large enough to accommodate misalignment during patterning. The dimensions of these active region result in large source/drain to substrate capacitances that seriously degrade the performance of the circuit. Furthermore, these conventional processing methods are unsuitable for fabricating devices of submicron size.
To overcome these problems, many schemes have been proposed to provide self-aligned source/drain contacts in submicron devices. These include various proposals for providing local interconnect layers, typically of TiN or polysilicon, to interface with a raised source and drain.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 5,804,846 (Fuller) that teaches a method for a self aligned elevated S/D by W layer and CMP.
U.S. Pat. No. 5,915,183 (Gambino et al.) shows a raised source/drain (S/D) process by a Poly etch.
U.S. Pat. No. 5,897,357 (Wu et al.) shows a process for a raised source/drain (S/D).
U.S. Pat. No. 5,422,289 (Pierce) shows another raised poly S/D process.
U.S. Pat. No. 6,015,727 (Wanlass) teaches a damascene S/D process.
However, the prior art process can be improved upon.